As efforts to extend usable time of batteries in mobile handsets, repeaters and base stations used for mobile communications while they are getting more miniaturized and multifunctional, lots of researches have been done recently to improve the efficiencies of RF power amplifiers that occupies most of the power consumption. Especially, researches on a Doherty power amplifier as one of typical schemes for enhancing the efficiency of a power amplifier are actively progressing.
As well-known in the art, a Doherty power amplifier, which was first designed in 1936 by W. H. Doherty, has a structure that connects a carrier amplifier and a peaking amplifier in parallel by using a quarter-wave transformer, i.e., a λ/4 line. The Doherty amplifier is driven by a symmetrical power coupling method that controls a load line impedance of the carrier amplifier by changing an amount of a current supplied from the peaking amplifier to the load according to a power level to thereby improve the amplification efficiency.
When designing a Doherty amplifier for use in mobile communications, a limitation in size thereof is getting more important, and there is a trend of the Doherty amplifier getting more miniaturized. However, conventional methods for implementing such Doherty amplifiers have drawbacks of high production costs due to the sizes of the chips and the packages thereof. Most noticeably, quarter-wave transformers for controlling load line impedances of carrier amplifiers and 3 dB 90° hybrid splitters for dividing input powers are major causes of the increase in the production cost of a Doherty amplifier for use in mobile communications.
FIG. 1 shows a conventional Doherty power amplifier, wherein a λ/4 π-network 50 configured with an inductor (L) and two capacitors (C) is employed as a quarter-wave transformer.
As shown therein, input matching circuits 20 and 25 are connected to input ends of a carrier amplifier 30 and a peaking amplifier 35, respectively, and output matching circuits 40 and 45 are connected to output ends thereof, respectively.
In this configuration, a 3 dB 90° hybrid splitter for dividing an input power is omitted to downsize the Doherty power amplifier. Herein, the input end of the carrier amplifier 30 keeps connected with that of the peaking amplifier 35, and the first delay circuit 55 is added between the power splitter 10 and the input end of the peaking amplifier 35 in order to match delays between the peaking amplifier 35 and the carrier amplifier 30, and a λ/4 π-network functioning as a quarter-wave transformer is used as the first delay circuit 55.
Further, an offset line 60 is connected to an output end of the output matching circuit 45 to set an output impedance to the peaking amplifier 35 to be infinite, thereby preventing power leaking from the carrier amplifier 30 to the peaking amplifier 35 instead of being delivered to the load at a low power level. If a phase of the offset line 60 is ∠θP, the first delay circuit 55 is set to be a λ/4−∠θP π-network at the input end of the peaking amplifier 35.
However, a conventional Doherty amplifier as described above is difficult to be integrated on a single chip because of its size and the inductor loss. Therefore, in most cases, a Doherty amplifier is implemented by a PCB (Printed Circuit Board) package. However, this scheme still has drawbacks in that the package size thereof and the number of passive devices used therefor are relatively large, thereby increasing the production cost thereof.
Further, other approaches have also been proposed in order to prevent the problems when using a 3 dB 90° hybrid splitter for dividing an input power. For example, some approaches are to modify the structure of the Doherty amplifier into a bypass type structure by using a switch, and others are to employ an active phase distributor. However, such endeavors also fail to present satisfactory solutions to overcome the above problems. In the meantime, for an ideal operation of a Doherty amplifier for use in a base station, it is required for the input power not to be divided identically to the carrier and the peaking amplifiers with a power level of 3 dB at a higher power level, but to be divided such that a slightly higher power is applied to the peaking amplifier than to the carrier amplifier at the higher power level. However, the above-mentioned conventional techniques cannot meet such requirements.